1. Field of the Invention
The present invention is related to a flash memory apparatus; in particular, to a flash memory apparatus which automatically switches the memory interface mode when operating with different types of flash memories.
2. Description of Related Art
Refer now to FIG. 1, which shows schematic block diagram of a prior art flash memory apparatus. As illustrated, the flash memory apparatus 9 comprises a plurality of flash memories 91, a controller 92 and a system interface 93. Herein the flash memory 91 can be for example of type of NAND flash memory, and the controller 92 is connected to an application system (not shown) through the system interface 93; e.g. a personal computer, a notebook computer, an industrial computer, a portable multimedia player, a digital camera, a digital recorder, and so forth. Also, the system interface 93 may be a parallel ATA interface (PATA), a serial ATA interface (SATA), a CompactFlash interface, a PCI-Express Interface, and a USB interface etc.
The controller 92 is connected to the flash memory 91 through at least a memory interface 921 and 922 (or referred as a channel), and each channel can be respectively connected to at least a flash memory 91. Furthermore, the controller 92, in terms of each memory interface 921 and 922, respectively provides a control signal 923 and 924 to control each flash memory 91. FIG. 1 shows a controller 92 of a dual channel.
Since the interface access speed of NAND-typed flash memory may differ due to factors such as manufacturer, capacity and fabrication process, there often is a design of adjustable memory interface access speed provided in the memory interface of the prior art flash memory controller. That is, the controller can identify the type of flash memory by means of reading the maker code of the flash memory and the device code of the flash memory itself, and can select suitable interface access speed. For example, if the memory interface access speed of the controller supports three different speeds, 70 ns, 50 ns, 25 ns (for reading or writing the trigger signal width indicator—represented by RE# or WE# enable signal width), the controller needs first to access the flash memory at the lowest speed (70 ns), identifies its code, confirms the interface access speed range supported by the flash memory, then it adjusts the interface circuit of the flash memory for tuning the interface timing, so as to select the highest access speed within the range supportable by the flash memory. In this way, it can avoid data errors caused by the interface access speed exceeding the supportable range of the flash memory; also, avoid the effect of under-performance of the flash memory apparatus access efficiency due to excessively low interface access speed.
Besides the difference in interface timing, with an effort to accelerate transmission speed of the memory interface, the industry has also proposed several new specifications, as well as standards for detecting and setting various interface modes. For example, the Open NAND Flash Interface (ONFI) standard lists, in addition to the back-compatible basic interface mode (Mode 0), five other different interface access modes; i.e. Mode 1˜5. Among them, there are two types of interfaces whose action mode for signal access further support Extended Data Out (EDO) mode, in order to increase data transmission stability in the course of high speed access action.
Furthermore, in hybrid density flash memory apparatus, the flash memory in use may comprise two or more different types of flash memories. For instance, the memory fabrication technology for holding single bit data is referred as Single-Level-Cell (SLC) process, and the fabricated memory is known as Low Density Memory; meanwhile, the memory fabrication technology for holding multiple bit data is referred as Multi-Level-Cell (MLC) process, and the fabricated memory is known as High Density Memory. In this case, since the controller is simultaneously connected to two or more different types of flash memories, and although the memory interface of the controller can adjust its interface mode or interface timing, single interface can only be configured as one mode and one timing at one time. If one interface is connected to two or more different types of flash memories at the same time, then, after detecting and identifying the above-mentioned memories, the controller must select only the mode which is simultaneously supported by both types of memories for access (i.e. usually the slowest one). Or, each time before changing the access object, the controller must first adjusts the settings of the memory interface, which modifies the interface settings to the mode supported by the flash memory about to be accessed.
However, for the aforementioned operations, no matter it is selecting the use of the access mode commonly supported by all flash memories connected to the same interface (usually the slowest one), or frequently changing the settings of the memory interface before access to the memory, neither can achieve the objectives of fully exploiting the access efficiency of the flash memory apparatus and, at the same time, avoiding the problem of data errors.